The present invention relates to integrated circuits, and more particularly to high voltage CMOS transistors.
A general trend in CMOS logic is to provide smaller transistors with minimum feature sizes and lower power supply voltages. This scaling of CMOS transistors allows for the incorporation of more devices onto the same area of silicon. It also allows for lower power operations and greater reliability because the electric field is reduced. As the power supply voltage is scaled down, peripheral requirements of the transistors such as field isolation, junction breakdown voltages, and punch-through voltages are also reduced.
However, some CMOS technologies, particularly those involving nonvolatile memory such as EEPROM, EPROM, Flash, antifuse technologies, and the like, require the use of high voltages internally. For example, some programmable logic devices (PLDS) include nonvolatile memories that use high voltages for programming and erasing the memories. Altera Corporation in San Jose, Calif. produces some exemplary PLDs with this characteristic.
Typically, these devices use high voltages ranging from about 9 volts to about 16 volts. These high voltages are used for programming and erasing the programmable memory cells. High voltages may also be used to improve the performance of the speed path of the integrated circuit. The high voltage requirements of these technologies do not scale as easily as their counterparts in logic CMOS technology. For example, some of these technologies use the same 9 to 16 volt range of high voltage to program and erase memory cells, even if the supply voltage is scaled down. Therefore, the requirements for high junction breakdown voltages, high transistor punch-through voltages, and high field isolation voltages continue to exist even when the transistor feature sizes are reduced.
In mixed-mode applications logic CMOS devices are integrated with nonvolatile CMOS memory devices. In these applications, simultaneous high voltage and low voltage requirements exist. These simultaneous requirements are often contradictory. For example, high voltage transistors with high junction breakdown characteristics and high punch-through characteristics are needed to pass the high voltage. At the same time, in order to efficiently pass the high voltage from source and drain, without significant voltage drop, the transistor should have low channel doping to minimize the so-called body effect. In previous generations of technology using looser design rules, these contradictory high voltage requirements were met using long channel length transistors. However, as the technology is scaled down to 0.35 xcexcm effective channel length (Leff) and beyond, the cost and difficulty of integrating these high voltage transistors is increased.
As can be seen, there is a need for high voltage tolerant transistors and devices, especially for use in integrated circuits where high voltages are used internally.
It is desirable to provide a technique for obtaining a set of minimum channel length transistors in a CMOS technology for both high and low voltage use. The native high voltage transistors in the set should preferably maintain high punch-through characteristics. Preferably, the transistors in the set will have the same minimum channel length. Designing all the transistors in the set to the same minimum channel length allows the design rules to be simpler, provides matching devices, simplifies the modeling of the transistors, and allows layout in a smaller area than long channel devices. It is desirable that such technologies be useful for 0.35 xcexcm effective channel length process technology and beyond. Further, the techniques to obtain these devices are preferably implemented without using any additional masks.
Consequently, the present invention provides an improved transistor for an integrated circuit. The transistor comprises source and drain regions in a substrate defining a channel region between them. The source and drain regions are separated by a channel length. A plurality of pocket implants, also known as xe2x80x9chalo implants,xe2x80x9d extend into the channel region between the source region and the drain region to cause a reverse short channel effect for the transistor.
The present invention also provides a method of fabricating an integrated circuit comprising the steps of depositing a field implant, depositing a well implant, and depositing an enhancement implant, wherein the steps of depositing a field implant, depositing a well implant, and depositing an enhancement implant are done using a single mask.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.